An Optimal Algo-Tech-Cuit for the Knapsack Problem

We present a formal derivation and proof of correctness of a systolic array for the knapsack problem, a well known, NP-complete problem. The dependency graph of the algorithm is not completely known statically, so the derivation also serves as a case study for systolic synthesis for this class of programs. The array is itself important since it achieves optimal performance on a model much weaker than a PRAM (ring of PE's with a xed size memory and only nearest neighbor interconnections). We show how the memory size of each PE can be chosen so that the running time is minimized by formulating and solving a non linear optimization problem. For this, we use the expected running time as the cost function and a register level model of VLSI. The original array has an intricate tag-based control mechanism which is diicult to implement. We show how this can be reduced to two simple counters and a few ip-ops. Coeecient loading is done with a multi-rate clock which avoids the need for shadow registers. These results show how it is important to use appropriate tools at diierent levels, and from diierent areas for designing application speciic array processors. Ces r esultats montrent que pour la conception de r eseaux sp eciiques l'importance, il est important d'utiliser les outils appropri es a chaque niveau de sp eciications, ces outils faisant appel a des techniques vari es.